1. Field of the Invention
The present invention generally relates to a row active control circuit of a pseudo static random access memory (hereinafter, abbreviated as “PSRAM”), and more specifically, to an improved row active control circuit of a PSRAM for controlling a refresh timing when a refresh operation is performed before activation of a row path for embodiment of a page mode, thereby preventing mis-operations.
2. Description of the Prior Art
Generally, a dynamic random access memory (hereinafter abbreviated as “DRAM”) memorizes information as a type of charges in a cell capacitor, transmits the charges, which is stored in the cell capacitor, to a corresponding bit line through an access transistor, and then amplifies the charges by a sensing amplifier to read data.
In the above-described DRAM, since a memory cell comprises an access transistor and a cell capacitor, the area occupied by the memory cell is small, so that a memory having a large memory capacity can be embodied with a small area.
Meanwhile, a memory device has been recently microscopic for high-speed operation of the memory device, for reduction of power consumption and miniaturization of the processing system. As a result, the area of the cell capacitor becomes smaller, and the capacity of the cell capacitor also becomes smaller. Although data having the same voltage level are inputted to the capacitor, the amount of sustaining charges becomes smaller if the capacity of the cell capacitor becomes smaller.
In order to compensate the reduction in the amount of sustaining charges, a refresh operation is periodically performed. In the refresh operation, data stored in the cell capacitor is transmitted to the bit line, amplified by the sensing amplifier, and then re-written in the cell capacitor.
As a result, when a data sustaining characteristic is degraded in the microscopic device, a refresh cycle is set to be short in order to compensate degradation of the data sustaining characteristic. However, when the refresh cycle is short, an external processing device is unable to access the DRAM during the refresh operation, thereby degrading performance of the processing system.
Also, when the refresh cycle is short, power consumption for the refresh operation increases. Specifically, the short refresh cycle does not meet a low standby current condition required in a data sustaining mode of a battery driving portable device, and cannot be applied to the battery driving portable device requiring low power consumption.
A PSRAM that operates the DRAM like a static random access memory (hereinafter, abbreviated as “SRAM”) has been known to solve the refresh problem of the DRAM. In the PSRAM, a cycle for performing read and write operations of common data and a refresh cycle for performing a refresh operation are successively performed in one cycle of a memory access cycle. That is, since the refresh operation is performed on one access cycle, the refresh operation can be hidden to an external access, so that the DRAM can be operated as the SRAM.
A row path in a general memory device includes serial processes for selecting a word line corresponding to a row address among a plurality of word lines, for transmitting data stored in a memory cell connected to the selected word line by sharing charges in a bit line, and for sensing the data in the bit line and amplifying the data at a level having a full swing width by a bit line sensing amplifier.
A column path in the memory device includes serial processes for selecting a memory cell corresponding a column address, and for externally outputting data in a bit line.
Generally, the row path is longer than the column path, so that it takes more time.
In order to solve the above-described problem, a page mode has been introduced to perform an effective read or write operation on the memory device. Here, the page means a memory cell which has the same word line in a different column address.
Both of the row path and the column path are not performed whenever data are stored or read in the memory cell. The row path is once performed at the initial stage in a different column address while a word line is activated, thereby enabling the read and write operation to be performed at a high speed.
FIG. 1 is a block diagram illustrating a refresh control circuit of a conventional PSRAM.
The refresh control circuit of FIG. 1 comprises a normal mode control unit 1, a refresh preventing control unit 2, a refresh detecting unit 4, a refresh initializing unit 6 and a refresh driving unit 8. Here, the refresh preventing control unit 2 includes a standby control unit 10 and a refresh wait control unit 11.
FIG. 2 is a circuit diagram illustrating the normal mode control unit 1 of FIG. 1.
The normal mode control unit 1 comprises inverters IV1 and IV2, a PMOS transistor PT1, a NMOS transistor NT1 and a latch unit LAT1.
The normal mode control unit 1 generates a normal mode control signal normalq in response to an address strobe signal add_stb and a precharge signal pcg.
When an address is changed, the address strobe signal add_stb is activated, so that the normal mode control signal normalq is activated to a high level by the PMOS transistor PT1.
Meanwhile, when the precharge signal pcg is activated, the normal mode control signal normalq is inactivated to a low level by the NMOS transistor NT1. Here, the latch unit LAT1 maintains the level state of the normal mode control signal normalq.
The standby control unit 10 of the refresh preventing control unit 2 generates a refresh standby state setting signal ref_standby when a self-refresh requiring signal srefreq is activated.
Here, when the precharge signal pcg is generated after a precharge or internal performance operation is externally completed, an idle state starts internally, so that a refresh operation can be performed.
A normal mode control signal normalq, which is generated when a row access performance is externally performed, requires a precharge period when an address is changed. Here, the refresh operation is prevented.
If the refresh operation is performed when the normal mode control signal normalq is generated, the refresh operation is performed in the precharge period to destroy cell data.
When the normal mode control signal normalq or a level signal natv_level is generated, the wait control unit 11 generates a wait signal so that the refresh operation may not be performed.
When the refresh operation is at the standby state, the wait signal is inactivated to a low level by the precharge operation and a level signal npcg_level delayed in the precharge operation is inputted, the refresh detecting unit 4 generates a refresh detecting signal ref_det to perform the refresh operation.
A refresh start signal ref_start is generated to have a high pulse depending on external row access. Here, if the level signal natv_level is required and the row access is faster than an internal refresh signal refb_int, the pulse of the refresh start signal ref_start is not generated, and the refresh operation is performed after the row access.
FIG. 3 is a block diagram illustrating a row active control circuit of a conventional PSRAM.
The row active control circuit of FIG. 3 comprises a row active signal generating unit 12, a precharge signal generating unit 14, a row active control unit 16 and an external active signal generating unit 18.
The row active signal generating unit 12 generates a row active signal rowact when an active condition is set.
The precharge signal generating unit 14 generates a precharge signal pcg when a precharge condition is set.
The row active control unit 16 generates a row active standby signal rowactq with the row active signal rowact in response to the precharge signal pcg.
The external active signal generating unit 18 generates an external active control signal extatv in response to the row actie standby signal rowactq.
FIG. 4 is a timing diagram illustrating the operation of the row active control circuit of FIG. 3. Here, an example when a word line W/L1 is refreshed is exemplified, so that an address AX is invalid.
First, when an external address is changed the precharge signal pcg is generated, the normal mode control signal normalq is located at the same time period.
When the normal mode control signal normalq and the precharge signal pcg are located at the same time period, an address strobe signal add_stb to receive the address is generated. Then, a row active signal rowact for generating an active signal extatv or intatv is generated.
Here, when the refresh signal refb is generated, the row active signal rowact becomes at a standby state, so that the row active standby signal rowactq is generated.
If the address is changed while the row active standby signal rowactq is enabled, the precharge signal pcg is generated to be reset. Here, an interval T1 between the address strobe signal addstb and the external active signal becomes short, so that more than two word lines W/L2 and W/L3 are activated as shown in FIG. 4. As a result, the normal operation cannot be performed or a characteristic margin is reduced.